EE硕士求ASIC职位内推。顺便求还坚守在EE的各位同胞们多多交流

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yanyan2060
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如题,求ASIC相关职位内推。
个人基本情况:MSEE,东部水校SBU。GPA3.8。14年底就毕业了。。找工作开始的比较晚错过了1到3月。。除了CA的第一个project。。学校相关project面试官都不感兴趣。。到现在为止有回应的不多,然后4月到现在补了Computer Architecture 和System Verilog相关的验证知识和project。简历上project相关部分如下:
[align="left"]Dual-issuePipelined Multimedia Processor (Verilog) 02.2014—04.2014 [/align][align="left"] ; Designed a dual-issue pipelined multimediaprocessor based on the SONY Cell Synergistic Processing Unit [/align][align="left"] architecture to support SIMD functionality. [/align][align="left"] ; Processor could detect data hazard andcontrol hazard and solve them by forwarding and stalling. [/align][align="left"]Verificationfor a 2*2 Ethernet Switch (SystemVerilog) 04.2015—05.2015[/align][align="left"] ; Implemented RTL code based on FSM and FIFO for a 2*2 Ethernet switch. [/align][align="left"] ; Built a testbench including interface,generator, driver, monitor and checker and top level testbench. [/align][align="left"] ; Generated constraind-random stimulus andwrote the code for functional coverage.[/align][align="left"]Implementationof Caches Hierarchy (C++) 05.2015—06.2015 [/align][align="left"] ; Implemented4-way set-associative instruction and 8-way set-associative data L1 cache, a unified16-way [/align][align="left"] set-associativeL2 cache with 16 MSHRs.[/align][align="left"] ; Implemented LRU replacementpolicies by using double linked list and WBWA allocate policies.[/align][align="left"]Out-of-OrderPipeline with ROB based on Tomasulo’s Algorithm (C++) 05.2015—06.2015 [/align][align="left"] ; Modeled pipeline stages to performout-of-order execution and in-order retire[/align][align="left"] ; Utilized re-order buffer performing in-orderupdating of register files to ensure precise state.[/align][align="left"]Synchronous& Asynchronous FIFO Design and Verification (SystemVerilog) 04.2014—05.2014 [/align][align="left"] ; Implemented a synchronous FIFO and wrote theinterface, driver, scoreboard to verify it.[/align][align="left"] ; Implemented an asynchronous FIFO with fulland empty flag using Gray code pointer.[/align][align="left"]Four BitCarry Select Full Adder (Cadence Virtuoso) 11.2014—12.2014[/align][align="left"] ; Designed and verified a 4 bit carry selectfull adder using D flip-flop, multiplexer and mirror 1 bit full adder. [/align][align="left"] ; Used 1 stage pipelining for the full adderand obtain 421MHz clock frequency. [/align][align="left"] ; Used Cadence Virtuoso to draw the CMOSschematic and layout also passed DRC and LVS.[/align][align="left"]还用过SystemC写过一些project。。(根据之前仅有的几次回应感觉面试官不感兴趣就果断删掉了。。。),。用C++做过data mining 的算法(对找工作感觉木有啥用。。。。)[/align][align="left"]求地里的各位前辈如果觉得有合适的机会可以内推!!拜谢。。或者对我的简有什么[/align][align="left"]建议都欢迎提出!其实硕士阶段也修过算法什么的CS课程可是还是觉得对EE比较感兴趣。个人脑子不是那么聪明但也是一直会为自己目标努力奋斗的人,想再努力一把,[/align][align="left"]如果有同样坚持着硬件找工作的同学欢互相交流。 [/align][align="left"]我的linked in : https://www.linkedin.com/pub/yanyan-zhou/7b/112/2bb[/align][align="left"]联系邮箱:1point3acres.com[/align]
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