Apple内推
55707
Apple（我所在的组）招 ASIC Enginee，有好几个opening，非常希望国人加入！如果感兴趣请发简历至1point3acres.com. 简历楼主会筛选
一下，如果没问题可以直接递给hiring manager. 楼主是做硬件的，没法推荐软件的工作，抱歉～
如果是new grad，只需要名校＋high GPA，这样容易过简历关
如果是有经验的在职跳槽，需要design process 包括 coding micro
architecture synthesis timing CDC等等都有很好的理解
familiar with AXI protocol and design is a plus.
不需要太多的 data process knowledge but need to be excellent about control
flow and handshake
具体如下
Key Qualification:
RTL Logic Design experience of multi-million gate ASICs
Hands on experience in all aspects of the chip development process with
proficiency in front end tools and methodologies
Experience writing specifications and converting them to design
Experience with multiple clock domains and asynchronous interfaces
Experience or knowledge of sy1point3acres.com architecture, CPU & IP Integration, and
power and clock management designs is highly desirable
Ability to communicate effectively across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl or Tcl a plus
Job Description:
As an ASIC Design Engineer, you will have responsibilities spanning various
aspects of SOC design:
Write microarchitecture and/or design specifications
Design, implement, and debug complex logic designs
Integrate complex IPs into the SOC
Support all front end integration activities like Lint, CDC, Synthesis, and
ECO
Work with other engineers that are members of the SOC Design, SOC Design
Verification, Emulation, STA
公司常年招DV Engineer, General or Specific area 的都可以
一下，如果没问题可以直接递给hiring manager. 楼主是做硬件的，没法推荐软件的工作，抱歉～
如果是new grad，只需要名校＋high GPA，这样容易过简历关
如果是有经验的在职跳槽，需要design process 包括 coding micro
architecture synthesis timing CDC等等都有很好的理解
familiar with AXI protocol and design is a plus.
不需要太多的 data process knowledge but need to be excellent about control
flow and handshake
具体如下
Key Qualification:
RTL Logic Design experience of multi-million gate ASICs
Hands on experience in all aspects of the chip development process with
proficiency in front end tools and methodologies
Experience writing specifications and converting them to design
Experience with multiple clock domains and asynchronous interfaces
Experience or knowledge of sy1point3acres.com architecture, CPU & IP Integration, and
power and clock management designs is highly desirable
Ability to communicate effectively across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl or Tcl a plus
Job Description:
As an ASIC Design Engineer, you will have responsibilities spanning various
aspects of SOC design:
Write microarchitecture and/or design specifications
Design, implement, and debug complex logic designs
Integrate complex IPs into the SOC
Support all front end integration activities like Lint, CDC, Synthesis, and
ECO
Work with other engineers that are members of the SOC Design, SOC Design
Verification, Emulation, STA
公司常年招DV Engineer, General or Specific area 的都可以
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